Memory is an essential component to many electronic devices today, ranging from computers to televisions. In the past decade, common forms of memory have evolved from fast-page (FP) mode and extended data out (EDO) to SDR, DDR and DDR2, which has brought advanced architectures, faster speeds, higher densities and bandwidths, and lower supply voltages and power consumption. These significant advancements have combined to advance DRAM—and the computing market segments—to even higher performance levels.
In the year 2000, DDR SDRAM was introduced to the market. DDR technology doubles SDR data rate by transferring data on both the rising and falling edges of a clock cycle. With DDR, 2 bits per data line are transferred every clock cycle rather than the 1 bit per data line with SDR. To do this, 2 bits are accessed from the memory array for each data line on every clock cycle. This process is called 2-word or 2n-prefetch. Prefetch helps get speed at an evolutionary pace, improving yields and increasing performance. DDR2 SDRAM functions much like DDR SDRAM, but with new features that enable faster speeds. While DDR has a 2n-prefetch and DDR2 a 4n-prefetch, DDR3 has an 8n-prefetch. The internal data cycle time of DDR3 is one-eighth of the external clock rate, and the internal data bus width is 8 times the size of the external data bus width. With DDR3, 8 bits of data are moved from the memory array to the I/O buffer per data line on each core clock cycle. Other bandwidth-enhancing features include lower RTT (termination resistance) values to support higher data rates. DDR2 values start at 50 ohms, while DDR3 values start at 20 ohms. Because DDR3 has twice the bandwidth of DDR2, DDR3 speeds pick up where DDR2 leaves off. DDR3 speeds start at 800 Mbps and max out at 1,600 Mbps. When a 64 bit bus bandwidth is figured in, DDR3 can reach speeds of 6,400 to 12,800 Mtransfers/s. A similar evolution has occurred for SRAM.
FIG. 1 shows a top level block diagram of the interaction between a controller 110 and an SRAM 120. Generally, a controller 110 is electrically coupled to a Common Input/Output SRAM 120 (CIO SRAM) through a plurality of traces on a circuit board (not shown). A CIO SRAM is capable of both receiving and transmitting signals via the same input/output port. Such a configuration reduces both surface area of an integrated circuit and power consumption, which are the two greatest considerations in efficient circuit design. The controller 110 sends clock, address and control signals to the SRAM 120. In some embodiments, a data signal is bidirectional between the controller 110 and the SRAM 120. Alternatively, the Data signal is coupled from the SRAM 120 to elsewhere in the system and is independent of the controller.
FIG. 2 shows a Programmable Impedance Output Driver (PIOD) 200. Such a PIOD 200 is typically implemented by the SRAM to drive data output signals. The PIOD comprises at least one fixed pull-up device 210 which is electrically coupled to a power source VDDQ. The fixed pull-up device 210 is enabled when the SRAM drives an output signal “high.” The PIOD further comprises at least one fixed pull-down device 215. The fixed pull-down device 215 is enabled when the SRAM drives an output signal “low.” It will be apparent to those of ordinary skill in the art of integrated circuit design that a signal “high” is generally equal to the voltage VDDQ minus an appropriate gate to source voltage drop for a signal “high” or the voltage VSS plus a gate to source raise for a signal “low”. Generally, the voltage VSS is ground, or zero. However, the voltage VSS is able to be a nonzero if the application requires. In this example, the fixed pull-up device 210 and fixed pull-down device 215 are both MOS transistors. The size of the fixed devices 210 and 215 is chosen such that when only one of the pull-up 210 or pull-down 215 devices are enabled the resulting driver impedance when measured from the output is greater than the maximum supported by the SRAM.
The PIOD 200 further comprises a bank of programmable pull-up devices 220 and a bank of programmable pull-down devices 230. Each device in the bank of programmable pull-up devices 220 is coupled to the voltage VDDQ and each device in the bank of programmable pull-down devices 230 is coupled to the voltage VSS. In the configuration described in FIG. 2, the pull-up devices 220 are binary weighted, meaning that the programmable pull-up device 220A is sized and configured to have a predetermined strength X, and each successive programmable pull-up device has a strength determined by X(2N) where N=1, 2, 3 and so on such that the device 220A has a strength of X, the device 220B has a strength of 2X, the device 220C has a strength of 4X, and so on. The bank of programmable pull-down devices 230 is configured in a similar fashion, such that device 230A has a strength of X, the device 230B has a strength of 2X, the device 230C has a strength of 4X, and so on. When an individual programmable pull-up device 220A-D or pull-down device 230A-D is enabled, the impedance value of that device is measurable from the output. Said differently, that impedance value is able to be measured from the output. The total size of all programmable devices is chosen such that when all of the fixed and programmable devices are enabled, the resulting driver impedance is less than or equal to the minimum supported the SRAM. Furthermore, the size of the smallest programmable device is chosen such that the ratio of its size to the total size of all fixed devices meets the driver impedance programming resolution accuracy target of the SRAM.
The output impedance of the PIOD 200 is able to be varied with a calibration circuitry 250 coupled to a reference impedance RQ 255. The reference impedance RQ 255 is typically an external resistor set by an end user as a reference point for the driver strength. When the various pull-up devices 220A-D or pull-down devices 230 A-D are enabled, the output impedance is an integer fraction or a multiple of RQ. Typically, and as a matter of convention, in high-speed synchronous SRAMs, the pull-up and pull-down driver impedance is equal to the value RQ/5. The typical range of driver impedance supported varies from 25Ω˜35Ω (min) to 45Ω˜60Ω (max). Generally, an output pre-driver 285 is used to buffer outgoing signals before transmission.
Similarly, the Programmable Input Termination (PIT) 300 shown in FIG. 3A has fixed pull-up devices 310 and fixed pull-down devices 315 along with a bank of variable pull-up devices 320 and pull-down devices 325. Termination impedance is able to be programmed any number of ways. Typically, an SRAM has a dedicated input pin (not shown) that the user connects to the voltage VSS through a reference resistor RT 321. The SRAM then uses a calibration circuit to determine which of the programmable pull-up devices to enable, in order for the resulting input “high” termination impedance to be equal to (or some specified fraction or multiple of) the termination impedance RT or which of the programmable pull-down fingers to enable, in order for the resulting input “low” termination impedance to be equal to (or some specified fraction or multiple of) the termination impedance RT. Typically, in high-speed synchronous SRAMs pull-up and pull-down termination impedance is equal to the termination impedance RT and the range of termination impedance supported varies from three to four times the range of driver impedance supported. In some applications, an input receiver 381 buffers signals for robust transmission within an integrated circuit.
FIG. 3B shows a separate driver and termination circuit 350. The circuit 350 comprises a driver portion 355 and a termination portion 360. The circuit 350 is able to be switched between driver and termination modes by external controls, thus saving space on a silicon chip. However, by essentially putting the two portions in series with an input/output point 370, all capacitances of all pull-up and pull-down devices are measurable from the input/output point 370, causing an overall detrimental effect on the maximum data transfer rate achievable.
An improvement over the solution of FIG. 3B is shown in FIG. 3C. A common output driver and input termination circuit 380 comprises a fixed portion 381 and a programmable portion 382. In this example, the output driver impedance range supported is between 25Ω and 50Ω. As mentioned above, the reference impedance RQ is usually five times greater than the supported range, or 125Ω to 250Ω. The input termination impedance range needed to be supported is approximately 120Ω˜180Ω and the termination impedance RT is 120Ω˜180Ω. The same circuit is duplicated to calibrate output driver strength and input termination strength. The circuit calibrates an impedance range equal to the union of the reference impedance RQ and the termination impedance RT ranges (120Ω˜250Ω). Therefore, the effective termination impedance range supported (120Ω˜250Ω) is 5 times the effective driver impedance range supported (24Ω˜50Ω). It is important to note that for the input termination, this solution offers a far greater range than is actually needed. The greater and unnecessary range directly correlates to a greater capacitance measurable from the input/output which has detrimental effects on the fastest possible data transfer. The reason for the excess range comes from the topography. The circuit 383 comprises one fixed pull-up device 383A and pull-down device 383B along with six programmable, binary-weighted pull-up and pull-down devices, and produces 6-bit binary pull-up and pull-down enable codes. The size of the fixed devices 381A and 381B in the fixed portion 381 is determined by the size of the fixed devices 383A and 383B in the impedance calibration circuit. The fixed devices 381A and 381B are enabled when the circuit 380 is functioning as an output driver only. The programmable portion 382 of the combined output driver input termination comprises nine binary weighted pull-up and pull-down devices 382A-I. The size of these programmable devices is determined by the size of the programmable devices used in the impedance calibration circuit 383. The six bit pull-up and pull-down enable codes produced by the driver impedance calibration circuit are applied directly to the six largest programmable devices (the 6 MSB devices) to best correlate the impedance of the driver to an external termination RQ. A 4-bit binary code (specifically, “1100”) equal to the relative strength of the fixed devices used in the impedance calibration circuit is added to the 6-bit pull-up and pull-down enable codes produced by the termination impedance calibration circuit. The sum is then divided by 5, since the effective termination strength range is 5 times the effective driver strength range and the 7 most significant digits of the result were then applied to the 7 smallest programmable devices, to create the input termination. In this way, the programmable devices are used to create both the programmable and fixed portions of the input termination. In effect, in termination mode, the fixed impedance portion is rolled into the programmable portion.
While the total Input/Output capacitance of this common solution was less than it would have been had a separate solution been used, it is not minimized. Also, dividing the six bit pull-up and pull-down enable codes produced by the termination impedance calibration circuit 383 by five before applying them to the appropriate programmable pull-up and pull-down devices, degrades the programming resolution accuracy of the termination impedance, because the result of the division is rounded and rounding introduces additional error in the accuracy of the impedance.